The present disclosure relates generally to analyzing a hardware device in connection with a computer system. More particularly, the present disclosure relates to sharing an interface of an integrated circuit among multiple partitions of the integrated circuit.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
In the 1980s, integrated circuits were becoming commonplace. However, testing circuit boards that included the integrated circuits for faulty connections (e.g., due to imperfections in solder joints on the circuit boards, board connections, or bonds and bond wires from integrated circuit pads to pin lead frames) was difficult because the connections were unavailable to testing probes. The Joint Test Action Group (JTAG) standard (IEEE standard 1149.1) was developed to provide an interface on or between integrated circuits to discover these faults.
For a field programmable gate array (FPGA), a single standard JTAG interface is extended to a core fabric of the FPGA to build JTAG-based logic. Specifically, for an FPGA, a single JTAG hub is created in the core fabric to enable multiple instances of JTAG-based logic to share the single JTAG interface. However, an FPGA may be physically divided into multiple partitions, for example, to implement partial reconfiguration. While the single hub may be created in the core fabric of a partition (e.g., a root partition of the FPGA) to enable JTAG-based logic in the root partition to share the single JTAG interface, if JTAG-based logic were also created in other partitions of the FPGA, such JTAG-based logic would be unable to share the single JTAG interface.